ISO 7816-3 PDF

There is currently a proposed revision to the ISO to remove ambiguities and to ensure an effective method of operation for changing the protocol type. An APDU is an Application Protocol Data Unit, a TPDU a Transport Protocol Data Unit. If an APDU command response pair has been defined for T=0 and it has. ISO/IEC specifies the power and signal structures, and information exchange between an integrated circuit card and an interface device such as a.

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This part describes electronic signals and transmission protocols of integrated circuit cards.

We copied it from an older version that is available on the Internet. If you have suggestions or material to include tables, graphs etc please contact us. The document will stay at this location for anyone that wants a direct link to this part of the standard.

We will edit this document as necessary to bring it up to date and add comments. Most of ISO is important for reader manufacturers or developers who want to establish a communication with a smart card on a very low level the signal level. There are many tools out there to read an ATR.

Input or Output for serial data to the integrated circuit inside the card.

Programing voltage input optional use by the card. Clocking or timing signal optional use by the card. Either used itself reset signal supplied from the interface device or in combination with an interal reset control circuit optional use by the card. If internal reset is implemented, the voltage supply on Vcc is mandatory. High level input voltage Vil: Low level input voltage Vcc: Power supply voltage at VCC Vpp: Programming voltage at VPP Voh: High level output voltage Vol: Low level output voltage tr: High level input current Iil: Low level input current Icc: Supply current at VCC Ipp: Programming current at VPP Ioh: High level output current Iol: Low level output current Cin: This contact is used as input reception mode or output transmission mode for data exchange.

When the two ends of the line are in reception mode, the line shall be maintained in state Z. When 7861-3 two ends are in non-matced transmit mode, the logic state of the line may be indeterminate.

During operations, the interface device and the card shall not both be in transmit mode. Two possible states exists for VPP: Idle state and active state, as defined in table 2. The idle state shall be maintained by the interface device unless the active state is required. Rise of fall time: The actual frequency, delivered by the interface device on CLK, is designated either by fi the initial frequency during the answer to reset, or by fs the subsequent frequency during subsequent transmission.

The dialogue between the interface device and the the card shall be conducted through the consecutive operations:. An active oso on VPP should not only be provided and maintained when requested by the card.

The electrical circuits shall not uso activated until the contacts are connected to the interface device so as to avoid possible damage to any card meeting these standards. The activation of the contacts by the interface device shall consist of the consecutive operations:. Isso card reset is initiated by the interface device, whereupon the card shall respond with an Answer to Reset as describe in 2. The clock signal is applied to CLK at time T0. An internally reset card reset after a few cycles of clock signal.


A card with an active low reset is reset by maintaining RST in state L for at least 40 clock cycles t3 after the clock signal is applied on CLK time t3 after T0.

If the Anwser to Reset does not begin within 40 clock cycles t3 with RST in state H t3 after T1the signal io RST shall be returned to state L at time T2 and the contacts shall be desactivated by the interface device.

With a card answering synchonously, the interface device sets all the lines to state L See figure 2. The clock pulse is applied after an interval t10 from the rising edge of the reset signal. The duration of the state H of the clock pulse can be any value between 10 us and 50 us ; no more than one clock pulse during reset high is allowed.

Therefore the design of the card has to avoid inproper operation. The priority of testing for asynchronous or synchronous cards is not defined in this standard. When informations exchange is terminated or aborted unresponsive card or detection of card removalthe electrical contacts shall be desactivated.

Each character includes an 8bit byte.

In order to read the initial character TSall cards shall initially be operated with fi in the range of 1 MHz to 5 MHz. A data byte consists of 8 bits designated b1 to b8, from the least significant bit lsb, b1 to the most significant bit msb, b8. The time origin being the mean between last observation of level Z and first observation of level A, the start shall be verified before 0. Parity is checked on the fly. When searching for a start, the sampling time shall be less than 0.

During the Answer to Reset, the delay between the start leading edges of two consecutives characters from the card shall not exeed etu.

This maximum is named initial waiting time. The disputed character shall be repeated after a delay of at least 2 etu after detection of the error signal. When parity is incorrect, from The receiver then shall expect a repetition of the disputed character see figure 8.

If no character repetition is provided by the card, — The card ignores and shall not suffer damage from the error signal coming from the interface device.

The interface characters specify physical parameters of the integrated circuit in the card and logical characteristics of the subsequent exchange protocol. The historical characters designate general information, for example, the card manufacturer, the chip inserted in the card, the masked ROM in the chip, the state of the life of the card. For national simplicity, T0, TAi, … ,TCK will designate the bytes as well as the characters in which they are contained.

Structure of TS, the initial character ————————————— The initial character TS provides a bit shynchronisation sequence and defines the conventions to code data bytes in all subsequent characters.

ISO part 3 smart card standard

These conventions refer to ISO This allows the interface device to determinate the etu initially used by the card. An alternate measurement of etu is a third of the delay between the first two falling edges in TS. Transmission and reception mechanisms in the card shall be consistent with the alternate definition of etu. The two possible values of TS ten consecutive bits from start to bi and corresponding hexadecimal value are.


Structure of the subsequent characters in the Answer to Reset ————————————————————- The initial character TS is followed by a variable number of subsequent characters in the following order: The presence of the historical characters is indicated by the number of bytes as specified in the format character defined below.

TDi indicates the protocol type T and the presence of subsequent characters. When needed, the interface device shall attribute a default value to information corresponding to a non transmitted interface character. Protocol type T ————— The four least significant bits of any interface character TDi indicate a protocol type T, specifying rules to be used to process transmission protocols.

Specifications of the global interface bytes ——————————————— Among the interface bytes possibly transmitted by the card in answering to reset, this subclaus defines only the global interface bytes TA1,TB1, TC1, TD1. These global interface bytes convey information to determine parameters which the interface device shall take into account.

ISO/IEC 7816

This initial etu is used during answer to reset is replaced 78116-3 the work etu during subsequent transmission. F is the clock rate conversion factor and D is the bit rate adjustment factor to determine the work etu in subsequent transmissions. I and P define the active state at VPP.

N is an extra guardtime requested by the card. No extra guardtme is used to send characters from the card to the interface device. TA1 codes FI over the most significant half byte b8 to b5 and DI over the least significant half byte b4 to b1. The most significant bit b8 equals to 0. PI1 from 5 to 25 gives the value of P in volts. Other values of PI1 are reserved for future use.

When PI2 is present, the ido of PI1 should be ignores. PI2 from 50 to gives the value of P in 0. Other isl of PI2 are reserved for future use. N codes directly the extra guard time, from 0 to etu. Any clock frequency between 7kHz and 50kHz may be chosen for the reset sequence. The header has a fixed length of 32 bits and begins with two mandatory fields of 8 bits, H1 and H2. The chronological order of transmission of information bits shall correcpond to bit identification b1 to b32 with the 78163 significant bit transmitted first.

The numerical meaning corresponding to each information bit considered in isolation is that of the digit. The first clock pulse is applied between kso and us t14 after the falling edge on RST to read the data bits from the card.

ISO Introduction

State H of the clock pulses can be varied between 10us and 50us t15 and state L between 10us and us t The following data bits are valid 10us t17 at least after is falling edge on CLK. Each data bit is valid until the next falling edge the following clock pulse on CLK. The data bits can therefore be sampled at the rising edge 781-3 the following clock pulses.

If there is no compatibility, the contacts shall be desactivated.